1. Field of the Invention
The present invention relates to a field effect transistor type ferroelectric nonvolatile storage element using a ferroelectric body at a control gate and a method of fabricating the same.
2. Description of the Related Art
As a field effect transistor type ferroelectric nonvolatile storage element using a ferroelectric body at a control gate, there is MFS-FET (Metal-Ferroelectric-Semiconductor-field effect transistor) (or conductor layer-ferroelectric layer-semiconductor-field-effect transistor) having a constitution of replacing an oxide film constituting an insulating layer of normal MOS-FET (Metal Oxide Semiconductor-Field Effect Transistor) (or conductor layer-oxide film-semiconductor-field effect transistor) by a ferroelectric body. According to the MFS-FET type memory, there is provided a method in which polarization of a ferroelectric body changes threshold voltage of the transistor and a change in resistance of a channel between a source and a drain is read as a change in the magnitude of a drain current value. According to the system, there is constituted so-to-speak nondestructive reading in which information is not destructed by reading operation at low voltage since ON/OFF of FET (field effect transistor) is maintained by holding residual polarization of the ferroelectric body.
A field effect ferroelectric memory transistor (MFS-FET) arranging a ferroelectric body at a control gate is classified into two kinds in gross classification. One of them is a ferroelectric transistor having a structure of MFIS (Metal-Ferroelectric-Insulator-Semiconductor) (or conductor layer-ferroelectric layer-insulator layer-semiconductor), in which an insulating layer (I) is sandwiched between a ferroelectric layer (F) and a semiconductor (S) of an MFS structure. The ferroelectric body induces electric charge at a surface of a semiconductor substrate via a gate insulating layer by polarization thereof.
Other thereof is a ferroelectric transistor having a structure of MFMIS (Metal-Ferroelectric-Metal-Insulator-Semiconductor) (or conductor layer-ferroelectric layer-conductor layer-insulating layer-semiconductor) as a gate structure, in which a conductor layer (M) (or referred to as floating gate) is sandwiched between a ferroelectric layer (F) and an insulating layer (I) of an MFIS structure. The present invention relates to the latter of the MFMIS structure.
Further, a conductor layer (M) described in the specification includes a conductor of polycrystal silicon (polysilicon, Poly-Si), an alloy of a metal and polycrystal silicon or the like other than a metal and a laminate thereof.
According to a conventional MFMIS type ferroelectric memory, as shown by FIG. 12A, there are formed a source region and a drain region by interposing a channel region on a semiconductor substrate (S), a main face of the middle channel region of the semiconductor substrate (S) is laminated with a silicon oxide layer (SiO2) frequently used in a semiconductor process as a gate insulator layer (I), polysilicon (Poly-Si) is laminated thereon as a first conductor layer (M), Ir/IrO2 (iridium/iridium oxide) is laminated further thereon as a barrier layer for preventing mutual diffusion between a ferroelectric material and Poly-Si, a ferroelectric thin layer (F), for example, PZT (PbZrXTi1xe2x88x92xO3) is laminated thereon and as a gate electrode, Ir/IrO2 is laminated thereon as a second conductor layer (M). FIG. 12A shows the laminated structure as a gate portion formed by carrying out lithography and etching. (A reference: T. Nakamura et al. Dig. Tech. Pap. of 1995 IEEE Int. Solid State Circuits Conf p.68 (1995))
FIG. 12B shows the MFMIS structure of FIG. 12A by an equivalent circuit and a capacitance (CF) of a ferroelectric capacitor and a capacitance (CI) of a gate insulator capacitor are connected in series. In FIG. 12B, when the ferroelectric layer is polarized by applying voltage between an upper electrode A and a semiconductor substrate B, it is necessary to apply the voltage until polarization of the ferroelectric body is sufficiently saturated in view of a memory holding characteristic.
Voltage distributed to the ferroelectric capacitor is dependent on a coupling ratio (CI/(CI+CF)) between the capacitance (CF) of the ferromagnetic capacitor and the capacitance (CI) of the gate insulator capacitor.
In order to enlarge the voltage distributed to the ferroelectric capacitor, it is important to design such that the capacitance (CI) of the gate insulating capacitor becomes larger than the capacitance (CF) of the ferroelectric capacitor.
Hence, in order to design to make the capacitance (CI) of the gate insulator capacitor larger than the capacitance (CF) of the ferroelectric capacitor, it is conceivable to thin the gate insulating film and thicken the ferroelectric thin film, however, there is a limit in thinning the gate insulating film in view of withstand voltage and leakage current. Further, when the ferroelectric thin film is thickened, high drive voltage is needed to saturate polarization of the ferroelectric body.
A conventional method for making the capacitance (CI) of the gate insulator capacitor larger than the capacitance (CF) of the ferroelectric capacitor while avoiding these problems, is a method of changing areas of the capacitance CF and the capacitance CI. FIG. 12C shows a simple schematic sectional view of carrying out the method. FIG. 12D shows a plain view viewing FIG. 12C from above. There is provided an MFMIS structure having a ferroelectric layer only at portion of an area of an MIS (conductor-insulator-semiconductor) portion for constituting CI. CI can be designed to be larger than CF as necessary by the conventional method.
However, according to the conventional method, in order to apply large distributed voltage on the ferroelectric capacitor, there is adopted the method of planarly enlarging the area of the MIS capacitor relative to the area of the MFM capacitor and therefore, as shown by FIG. 12D, even when the MFMIS portion is formed by a minimum fabrication dimension, the MIS portion is as large as an amount of an area ratio of the MIS portion and the MFMIS portion, as a result, a large area is occupied and there poses a problem that a high integration degree cannot be achieved.
Hence, the invention has resolved such an unresolved problem of the conventional technology. It is an object of the invention to provide a highly reliable transistor type ferroelectric nonvolatile storage element capable of realizing high density integrated formation by reducing a memory cell area.
In order to achieve the above-described object, according to a first aspect of the invention, there is provided a semiconductor nonvolatile storage element which is a ferroelectric nonvolatile storage element including a field effect transistor wherein the field effect transistor includes a structure successively laminated with a first insulator layer, a first conductor layer, a ferroelectric layer and a second conductor layer on a channel region of a semiconductor substrate, the field effect transistor includes a third conductor layer and a fourth conductor respectively formed on a source region and a drain region on both sides of the channel region of the semiconductor substrate, further comprising a second insulator thin film between the third conductor and the fourth conductor and the first conductor layer.
By constituting in this way, according to the first aspect of the invention, there is constructed a constitution in which a capacitor of an MIM structure constituted by the first conductor layer, the second insulator thin film and the third and the fourth conductors, is connected in parallel with a capacitor of an MIS structure constituted by the first conductor layer, the first insulator layer and the semiconductor substrate and accordingly, an effective area of the MIS structure can be increased and an electrostatic capacitance CI of a composite capacitor thereof can be increased.
Thereby, even when capacitor areas of the MFM structure and the MIS structure are provided with the same occupied area on a silicon main face, an effective area of the MIS structure can be made larger than an effective area of an MFM structure. Therefore, a coupling ratio (CI/(CI+CF)) of an electrostatic capacitance CF of the capacitor of the MFM structure to the composite electrostatic capacitance CI of the capacitor of the MIS structure and the capacitor of the MIM structure, can be increased without increasing the memory cell area as compared with related art example. Distributed voltage can efficiently be applied to a ferroelectric capacitor.
In this way, the effective area of the MIS capacitor laminated in an up and down direction substantially within the same area, can be made larger than the effective area of the MFM capacitor without increasing the occupied area. As a result, high density integrated formation can be realized by reducing the memory cell area and a highly reliable transistor type ferroelectric nonvolatile storage element can be provided.
According to a second aspect of the invention, there is provided the semiconductor nonvolatile storage element according to the first aspect wherein recesses and projections are included at a side wall of the first conductor layer opposed to the third and the fourth conductors and/or side walls of the third and the fourth conductors opposed to the first conductor layer.
By constituting in this way, according to the second aspect of the invention, the capacitance of the MIM structure is increased by increasing a surface area thereof by providing the recesses and the projections at the side walls of the third and the fourth conductors and the first conductor layer opposed thereto via the second insulator thin film. By constituting in this way, the effective area of the MIS structure can further be increased.
Therefore, although the capacitor areas of the MFM structure and the MIS structure are provided with the same occupied area on the silicon main face, the effective area of the MIS structure can be made further larger than the effective area of the MFM structure. Therefore, the coupling ratio (CI/(CI+CF)) of the electrostatic capacitance CF of the capacitor of the MFM structure and the composite electrostatic capacitance CI of the capacitor of the MIS structure and the capacitor of the MIM structure, can further be increased without increasing the memory cell area as compared with related art example and the distributed voltage can efficiently be applied to the ferroelectric capacitor.
According to a third aspect of the invention, there is provided the semiconductor nonvolatile storage element according to the first or the second aspect wherein the semiconductor substrate is an SOI (Silicon On Insulator) substrate.
By constituting in this way, according to the third aspect of the invention, the field effect semiconductor device is constituted on silicon above the insulating substrate and therefore, a parasitic capacitance between the source and the drain and the silicon substrate is reduced and a high-speed transistor type ferroelectric nonvolatile storage element with low power consumption can be provided.
According to a fourth aspect of the invention, there is provided the semiconductor nonvolatile storage element according to any one of the first through the third aspects wherein an area of the second conductor layer above the ferroelectric layer is made smaller than an area of the ferroelectric layer.
By constituting in this way, the effective area of the MIS structure can relatively made larger than the effective area of the MFM structure. Therefore, the coupling ratio (CI/(CI+CF)) of the electrostatic capacitance CF of the capacitor of the MFM structure and the composite electrostatic capacitance CI of the capacitor of the MIS structure and the capacitor of the MIM structure can further be increased and the distributed voltage can efficiently be applied to the ferroelectric capacitor.
According to a fifth aspect of the invention, there is provided the semiconductor nonvolatile storage element according to any one of the first aspect through the fourth aspects wherein the second conductor layer is disposed above an element isolating region of the semiconductor substrate.
By constituting in this way, an increase in a degree of freedom of wiring can be achieved by disposing the second conductor layer at the element isolating region and accordingly, highly integrated formation of the semiconductor nonvolatile storage element can further be promoted.
According to a sixth aspect of the invention, there is provided the semiconductor nonvolatile storage element according to any one of the first aspect through the fifth aspects wherein each of the first insulator layer and the second insulator thin film comprises a layer of one material or a layer laminated with two or more of materials selected from a group consisting of SiO2 (silicon oxide), SiN (silicon nitride), SiON (silicon oxynitride), SiO2xe2x80x94SiN (ON film: siliconoxide-silicon nitride), SiO2xe2x80x94SiNxe2x80x94SiO2 (ONO film: silicon oxide-silicon nitride-silicon oxide), Ta2O5, SrTiO3, TiO2, (Ba,Sr)TiO3, Al2O3, ZrO2, HfO2, Y2O3, CeO2, CeZrO2 and YSZ (yttrium oxide stabilized zirconium oxide).
According to a seventh aspect of the invention, there is provided the semiconductor nonvolatile storage element according to any one of the first through the sixth aspects wherein the ferroelectric layer is a layer of one material selected from a group consisting of SrBi2Ta2O9, PbTiO3, PbZrxTi1xe2x88x92xO3, PbYLa1xe2x88x92YZrxTi1xe2x88x92xO3, Bi4Ti3O12, SrNbO7, Pb5Ge3O11 and Sr2TaxNb1xe2x88x92xO7.
According to an eighth aspect of the invention, there is provided a method of fabricating a semiconductor nonvolatile storage element which is a method of fabricating the semiconductor nonvolatile storage element according to the first aspect, the method comprising (a) a step of forming a dummy gate above a portion of a semiconductor substrate including a channel region, (b) a step of integrally depositing a third and a fourth conductor above the semiconductor substrate and above the dummy gate, (c) a step of flattening the third and the fourth conductors, (d) a step of forming a source region and a drain region at the semiconductor substrate, (e) a step of exposing the portion of the semiconductor substrate by removing the dummy gate, (f) a step of forming an insulator thin film above the exposed portion of the semiconductor substrate, above side walls of the third and the fourth conductors and above the third and the fourth conductors, (g) a step of successively laminating a first conductor layer, a ferroelectric layer and a second conductor layer above the insulator thin film, and (h) a step of patterning the second conductor layer and the ferroelectric layer and the first conductor layer and etching to form the second conductor layer, the ferroelectric layer and the first conductor layer.
According to the fabricating method of the eighth aspect of the invention, there is constructed a constitution in which a capacitor of the MIM structure constituted by the first conductor layer, the second insulator thin film, the third conductor layer and the fourth conductor layer, is connected in parallel with the capacitor of the MIS structure constituted by the first conductor layer, the first insulator layer and the semiconductor substrate, the effective area of the MIS structure can be increased and the electrostatic capacitance CI of the composite capacitor can be increased.
In this way, by providing the MFM structure formed by the second insulator thin film and the third and the fourth conductors at the side wall of the first conductor layer, the effective area of the total capacitor CI of a buffer layer can be made larger than the effective area of the MFM capacitor. Therefore, according to the fabricating method, in comparison with the conventional example, the coupling ratio (CI/(CI+CF)) of the electrostatic capacitor CF of the MFM capacitor and the composite electrostatic capacitance CI of the MIS capacitor and the MIM capacitor can be increased without increasing the memory cell area and the distributed voltage can efficiently be applied to the ferroelectric capacitor.
In this way, the area of the MIS capacitor laminated in the up and down direction substantially in the same area, can be made larger than the area of the MFM capacitor without increasing the occupied area and as a result, integrated formation can be realized at high density by reducing the memory cell area and the highly reliable transistor type ferroelectric nonvolatile storage element can be provided.
Further, according to the fabricating method, when the ferroelectric layer is formed at step (g), since the semiconductor substrate is not exposed, there is achieved an advantage that the device characteristic is prevented from being deteriorated by isolating an impurity included in the ferroelectric body and diffusing the impurity into the semiconductor substrate.
Further, normally, a source and a drain region is formed by forming a gate portion and thereafter implanting ions to a semiconductor substrate and subjecting the semiconductor substrate to an annealing, however, there is a concern of damaging a side wall of a ferroelectric thin film by implanting ions. Further, there is a concern of contaminating silicon by the ferroelectric body in the annealing. In contrast thereto, according to the fabricating method of the invention, the ferroelectric capacitor is formed after forming the source and the drain and therefore, there is an advantage that there is not a problem of damaging the side wall or contaminating the ferroelectric body.
According to a ninth aspect of the invention, there is provided a method of fabricating a semiconductor nonvolatile storage element which is a method of fabricating the semiconductor nonvolatile storage element according to the first aspect, the method comprising (a) a step of successively laminating a first insulator layer, a first conductor layer and an insulating layer for constituting a hard mask above a semiconductor substrate, a step of etching to form the insulating layer for constituting the hard mask, the first conductor layer and the first insulator layer in a predetermined pattern and a step of forming a source region and a drain region at the semiconductor substrate, (b) a step of forming a second insulator thin film at side walls of the first insulator layer, the first conductor layer and the insulating film, (c) a step of integrally depositing a third and a fourth conductor above the semiconductor substrate, above the insulating film, above the second insulator thin film and above a side wall of the second insulator thin film, (d) a step of flattening the third and the fourth conductors, (e) a step of forming an insulating layer above the third and the fourth conductors and a step of removing the insulating film for constituting the hard mask, (f) a step of successively laminating a ferroelectric layer and a second conductor layer above the insulating layer above the third and the fourth conductors and above the first conductor layer, and (g) a step of etching to form the second conductor layer and the ferroelectric layer by patterning the second conductor layer and the ferroelectric layer.
According to the fabricating method of the ninth aspect of the invention, by providing the MIM structure formed by the second insulator thin film and the third and the fourth conductors at the side wall of the first conductor layer, the effective area of the total capacitor CI of the buffer layer can be made larger than the effective area of the MFM capacitor. Therefore, according to the fabricating method, in comparison with the conventional example, the coupling ratio (CI/(CI+CF)) of the electrostatic capacitance CF of the MFM capacitor and the composite electrostatic capacitance CI of the MIS capacitor and the MIM capacitor, can be increased without increasing the memory cell area and the distributed voltage can efficiently be applied to the ferroelectric capacitor.
Further, when an impurity is implanted to the source region and the drain region formed at step (a) by utilizing the second insulator thin film formed at the step (b) as a spacer, an LDD (Lightly Doped Drain) structure can be formed.
According to a tenth aspect of the invention, there is provided a method of fabricating a semiconductor nonvolatile storage element which is a method of fabricating the semiconductor nonvolatile storage element according to the second aspect, the method comprising (a) a step of successively laminating a first insulator layer, a first conductor layer and an insulating layer for constituting a hard mask above a semiconductor substrate, a step of etching to form the insulating layer for constituting the hard mask and the first conductive layer in a predetermined pattern and a step of forming a source region and a drain region at the semiconductor substrate, (b) a step of forming recesses and projections at a side wall of the first conductor layer and a step of forming a second insulator thin film above the recesses and projections, (c) a step of removing the first insulator layer above the source region and above the drain region, (d) a step of integrally depositing a third and a fourth conductor above the semiconductor substrate, above the insulating film for constituting the hard mask, above the second insulator thin film and above a side wall of the second insulator thin film, (e) a step of flattening the third and the fourth conductors, (f) a step of forming an insulating layer above the third and the fourth conductors, (g) a step of removing the insulating film for constituting the hard mask, (h) a step of laminating a ferroelectric layer and a second conductor layer above the insulating layer and the first conductor layer, and (i) a step of etching to form the ferroelectric layer and the second conductor layer by patterning the ferroelectric layer and the second conductor layer.
According to the fabricating method of the tenth aspect of the invention, there is provided the MIM structure formed by the side wall of the first conductor layer and the second insulator thin film and the third and the fourth conductors and increasing the surface area by forming very small recesses and projections at the surface of the side wall of the first conductor layer. That is, according to the fabricating method, the capacitance of the MIM structure is increased by increasing the surface area by recesses and projections of the side wall of the first conductor layer at step (b) to thereby further increase the effective area of the MIS structure. As a result, the effective area of the total capacitor CI of the buffer layer can be made larger than the effective area of the MFM capacitor. Therefore, according to the fabricating method, in comparison with the related art example, the coupling ratio (CI/(CI+CF)) of the electrostatic capacitance CF of the MFM capacitor and the composite electrostatic capacitance CI if the MIS capacitor and the MIM capacitor can be increased without increasing the memory cell area and the distributed voltage can efficiently be applied to the ferroelectric capacitor.
According to an eleventh aspect of the invention, there is provided the method of fabricating a semiconductor nonvolatile storage element according to the tenth aspect wherein the (h) step includes a step of laminating a barrier layer above the insulating layer and above the first conductor layer before the step of laminating the ferroelectric layer and in the (i) step, the barrier layer is also etched to form by patterning the barrier layer.
According to the fabricating method of the eleventh aspect of the invention, the barrier layer can prevent movement of the impurity of the ferroelectric layer thereabove to the semiconductor substrate and stability of operation of the element can be maintained.
According to a twelfth aspect of the invention, there is provided a method of fabricating a semiconductor nonvolatile storage element which is a method of fabricating the semiconductor nonvolatile storage element according to the third aspect, the method comprising (a) a step of successively laminating an insulating layer and a dummy gate material above a semiconductor substrate, a step of etching to form the dummy gate and the insulating layer in a predetermined pattern and a step of forming a source region and a drain region, (b) a step of integrally depositing a third and a fourth conductor above the semiconductor substrate and above the dummy gate and a step of flattening the third and the fourth conductors, (c) a step of removing the dummy gate, (d) a step of removing the insulating layer and forming recesses and projections at side walls of the third and the fourth conductors, (e) a step of forming a first insulator layer above the semiconductor substrate and forming a second insulator thin film above the third and the fourth conductor layers and above the recesses and the projections of the side walls of the third and the fourth conductors, (f) a step of successively laminating a first conductor layer and a ferroelectric layer and a second conductor layer above the first insulator layer and above the second insulator thin film, and (g) a step of etching to form the second conductor layer, the ferroelectric layer and the first conductor layer by patterning the second conductor layer, the ferroelectric layer and the first conductor layer.
According to the fabricating method of the twelfth aspect of the invention, the effective area of the total capacitor CI of the buffer layer can be made larger than the effective area of the MFM capacitor by increasing the surface area by forming very small recesses and projections at the surfaces of the side walls of the third and the fourth conductors and forming the MIM structure by the side walls of the third and the fourth conductors and the second insulator thin film and the first conductor layer and connecting the MIM structure in parallel with the MIS structure. Therefore, according to the fabricating method, in comparison with the conventional example, the coupling ratio (CI/(CI+CF)) of the electrostatic capacitance CF of the MFM capacitor and the composite electrostatic capacitance CI of the MIS capacitor and the MIM capacitor, can be increased without increasing the memory cell area and the distributed voltage can efficiently be applied to the ferroelectric capacitor.